The current invention will, through a special two-time phase electrical communication protocol plus the synergistic utilization of all interconnected drivers in combination to charge the interconnecting bus lines, take a communication method previously found only on Very Large Scale Integrated Circuit (VLSIC) chip internal buses and expand such method and modify such method to allow high performance interchip communication--an area currently dominated by tri-state drivers. The discussion in the book "Introduction to VLSI Systems".COPYRGT. 1980 by Mead and Conway and published by Addison-Wesley is especialy pertinent to an understanding of prior art VLSIC interconnect. The Mead and Conway data, developed from the CalTech Silicon Structures Project, is related in substantially their own description in the following six paragraphs and associated FIGS. 1 through 3.
Mead and Conway's internal chip design incorporates two buses. For the dual reasons of the internal function of their interconnected blocks, such as an Arithmetic Logic Unit (ALU), and the unacceptable size of a tri-state driver, as will be shortly discussed, a two-phase electrical communication protocol is employed. The interconnected ALU of Mead and Conway performs its operation during the phase 2 (.phi.2) period and does not have valid data to place into its output register until the end of .phi.2. If data is to be transferred from the output register of the ALU to its input register, this must be done during the phase 1 (.phi.1) period. They adopt a standard timing scheme in which all transfers on the buses occur during .phi.1. Thus they can make use of the .phi.2 period when the ALU is performing its operation to precharge the buses and thereby solve what they describe as one of the knotty problems associated with a technology designed for ratio logic. If they had insisted that the tri-state drivers associated with various sources of data for a bus be able to drive up as well as down, they would have required both a sourcing and sinking transistor, together with a method for disabling both transistors. While it is perfectly possible to build such a driver, it is a space consuming matter to use such a driver at every point where it is wished to source data onto an internal bus. By using the bus precharge scheme the tri-state drivers of Mead and Conway become simply two series transistors as shown in FIG. 1.
FIG. 1 shows a precharged internal bus communication circuit. In FIG. 1, single transistor 102 charges bus line 103 during time phase 2 (.phi.2) from voltage source 104. During time phase 1 (.phi.1) the data from one source called Source 1, for example the ALU output register, is placed on the gate of one transistor of the pairs of series transistors, for example on transistor 106. An enable signal which may come high during .phi.1, called .phi.1. Enable One, is placed on the other one of the same series transistors; that is on transistor 108. If one and only one of the enable signals is allowed to come high during any one .phi.1 period, the bus can be driven from as many sources as necessary. The performance of such a bus is limited only by the pull-down capability of the two series transistors. For the purposes of the present invention it is important to note that only one transistor 102 precharges the internal bus line 103. FIG. 1 essentially shows a bus charging/discharging driver circuit. It is obvious that data would be gated off the bus by "receiver" gates at any location or locations only during .phi.1 while the bus is carrying information such as being driven in a wired-OR fashion.
Mead and Conway find communication with what they call the "outside world," such communication as is accomplished by the present invention, to be more difficult. Mead and Conway note that although in particular applications the interface from a port of the data path to the outside world may be a point to point communication, the ports will often connect to a bus. Thus it is desirable to use port drivers which may be set in a high impedance state. Drivers which can either drive the output high, drive the output low, or appear as a high impedance to the output are known as tri-state drivers. Such drivers allow as many potential senders on the bus as necessary.
FIG. 2 shows the circuit for the interface of a tri-state driver 202 to a contact pin or pad 205 which connects to an interchip communication bus. In FIG. 2 either chip internal BUS A on input 201 or chip internal or BUS B on input 203 can be respectively latched into the input of a tri-state driver 202 during .phi.1 by signal LATCH A.multidot..phi. on the gate of first gating transistor 204 or by signal LATCH B.multidot..phi. on the gate of second gating transistor 206. The receiver circuit as connects to connect pad 205 is not shown in FIG. 2 for being realizable with any number of essentially trivial implementations. Mead and Conway point out that pad 205 could be latched into the incoming register of any interchip communication bus connected device at any time independent of or asychronous to, the clock phases of the tri-state driver chip. As the present invention, however, adapts the two phase bus communication protocol as shown for internal bus line 103 in FIG. 1 to the external interchip communication bus line, as is connected to pad 205 in FIG. 2, the receiving, or latching, of data from the bus will be done only at a specified time, as was required in the internal bus communication scheme of FIG. 1. A sample trivial receiver circuit, an AND gate, which is, however, gated at a specific time, is shown in the DRIVER/RECEIVER circuit of FIG. 82 within U.S. patent application Ser. No. 356,051 which is incorporated by reference within this application. Such a gated AND gate, or the receiver part of the present invention of a VLSI Wired-OR DRiver/Receiver Circuit, is a known prior art method of receiving a signal from a bus, either asynchronously or synchronously with the driving of such bus. The concept and utility of the present invention must be compared to the prior art design of the tri-state driver 202 which drives the pad 205 directly. Details of the tri-state driver 202 are shown in FIG. 3.
The signals OUT and OUT as respectively occur on lines 207 and 209 of FIG. 2 are fed to a series of super buffer stages as illustrated in FIG. 3a, each of which provides true and complement signals as respective outputs 301 and 303 and each of which is disabled by a DISABLE signal on line 305. The DISABLE signal does not cause all current to cease flowing in the drivers, since the pullup transistors are depletion type, but reduces the current to a value where it can be handled by the disable transistor of the following buffer stage. In general there are a number of super buffer stages of this sort in a tri-state driver. The very last stage of the driver is shown in FIG. 3b. It is not a super buffer but employs enhancement mode transistors 302 and 304 for both pullup and pulldown. These transistors are very large in order to drive the large external capacitance associated with the wiring attached to the pad 205. They are disabled in the same manner as the super buffers, except that when the gates of both transistors are low, the output pad is truly tri-stated, meaning that naught but high impedance is presented to pad 205. The two output transistors 302 and 304 are a factor of approximately e (equals approximately 2.71828) larger than the transistors of last super buffer in the buffer string.
The series of super buffer stages necessary to transform the impedance from that of the internal circuits on-chip to that sufficient for driving a pad attached to wiring in the outside world is quite large, and imposes a delay of some factor times a logarithm of this impedance ratio upon communications between the chip and the outside world. Any help that can be obtained in making this transformation is of great value. For example, the latch and buffers associated with the input bus circuit to the pad drivers can themselves be graded in impedance level, so that by the time the OUT and OUT signals on lines 207 and 209 respectively are derived, they are at a considerably higher current drive capability than the buses. The buses are of considerably larger capacitance than the interconnection nodes on the chip, and thus the initial latch buffers can be larger than typical inverters on the chip. All such tricks help to minimize the number of stages between the buses and the output pad which drives the outside interchip communication bus, and thus the total delay in translating internal chip signals such as OUT and OUT into drive of the interchip communication bus line connected to pad 205.
A more complete explanation of these prior art techniques may be found in the indicated reference of Mead and Conway. The high drive current required for the interchip communication bus and resultant size problem for these VLSIC pad driver stage output transistors is very severe. If 37 pads were to be driven on each VLSIC chip and a one meter bus interconnecting 256 chips supported, the equivalent current transistors of the pad driver stage shown in FIG. 3b might be as large as 4.times.800 square microns for the N-type transistor 304 and 4.times.2400 square microns for the P-type. For a reasonable size VLSIC substrate this means that one-third of the available area is devoted to interconnecting lands, one-third to logics, and one-third to the two drive per bus line interface transistors. The present invention will later be seen to be much more economical in the interface transistor size required.